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[VHDL-FPGA-Verilog] FlashTime

Description: 用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。 -Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let the user know time revised. This module implements the similar function. It is one of my total 9 modules that are used to design a digital clock.
Platform: | Size: 143360 | Author: chzhsen | Hits:

[VHDL-FPGA-Verilog] Traffic-light-design

Description: (1) 能显示十字路口东西、南北两个方向的红、黄、绿的指示状态； • 用两组红、黄、绿三色灯作为两个方向的红、黄、绿灯，能实现正常的倒计时功能； • 用两组数码管作为东西和南北方向的到计时显示，显示时间为红灯55秒、绿灯50秒、黄灯5秒； *(2) 按S1键后，能实现特殊状态功能: • 显示到计时的两组数码管闪烁； • 计数器停止计数并保持在原来的状态； • 东西、南北、路口均显示红灯状态； • 特殊状态解除后能继续计数。 (3) 能实现总体清零功能按下SB键后，系统实现总清零，计数器由初始状态计数，对应状态的指示灯亮； (4) 用VHDL语言设计符合上述功能要求的交通灯控制器，并用层次化设计方法设计该电路； (5)控制器、置数器的功能用功能仿真的方法验证，可通过有关波形确认电路设计是否正确； *(6)完成电路全部设计后，通过系统实验箱下载验证设计课题的正确性。 -(1) to show intersections east and west in both directions of the red, yellow, green indicates the state • Use two sets of red, yellow, and green lights as the two directions of red, yellow, green, countdown to achieve normal function • Digital control with two north-south direction as to the things and time display, time display a red light 55 seconds, 50 seconds green, yellow 5 seconds * (2) Press the S1 key, to achieve a special state function: • Display to the timing of the two sets of digital flash • The counter stops counting and remains in its original state • east and west, crossing all red light status • Special lifting of the state can continue to count. (3) to achieve the overall SB Clear function key pressed, the system achieved a total cleared, the counter counts from the initial state, the corresponding status indicator light (4) using VHDL language design meets the functional requirements of the traffic light co
Platform: | Size: 10240 | Author: 薛静 | Hits:

[VHDL-FPGA-Verilog] Reading-User-Data-from-Proms

Description: FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring FPGA,reading and writing user data from flash,including the VHDL and Verilog code
Platform: | Size: 1418240 | Author: 赵齐 | Hits:

[VHDL-FPGA-Verilog] Using-JTAG-PROMs-for-data-storage

Description: Xilinx FPGA的配置中，从Flash中读写用户数据，包括VHDL、Verilog程序-in configuring Xilinx FPGA,reading and writing user data from flash,including the VHDL and Verilog code
Platform: | Size: 158720 | Author: 赵齐 | Hits:

[VHDL-FPGA-Verilog] 74serie-code

Description: 74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
Platform: | Size: 2755584 | Author: 赵亮兵 | Hits:

[VHDL-FPGA-Verilog] nand_flash_ctl

Description: NAND flash的VHDL控制代码，可以看一下-VHDL control code of NAND flash
Platform: | Size: 5120 | Author: 沈碧云 | Hits:

[VHDL-FPGA-Verilog] FLASH_read

Description: 对spi接口的flash操作，用VHDL语言实现，read控制，串行输入，可以1位、2位、4位读出-Spi interface on the flash operation, with the VHDL language, read control, serial input, to one, two, four read
Platform: | Size: 2048 | Author: 王伯祥 | Hits:

[Windows Develop] NRS_5_3_GF256A

Description: 用于NAND FLASH CONTROLLER 中的的 ecc 各个模块VHDL代码，已通过测试。 -For NAND FLASH CONTROLLER in ecc VHDL code of each module, has been tested.
Platform: | Size: 190464 | Author: yongjiu | Hits:

[VHDL-FPGA-Verilog] writereadflash

Description: 这个是用VHDL实现FPGA对FLASH的读写。-This is achieved using VHDL FLASH FPGA to read and write.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] NAND_flash_verilog_vhdl

Description: 很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。- NAND Flash Controller Reference Design =============================================================================== File List 1. RD1055/doc/rd1055.pdf --> NAND Flash Controller Reference Design document RD1055/doc/rd1055_readme.txt --> Read me file (this file) 2. RD1055/Project/nand_flash_cntl.lpf --> preference file for the design RD1055/Project/nfcm_tb_vhd.udo_example --> vital glitch removal example 3. /RD1055/simulation/verilog/rtl_verilog.do --> verilog rtl simulation script /RD1055/simulation/verilog/timing_verilog.do --> verilog timing simulation script /RD1055/simulation/vhdl/rtl_verilog.do --> vhdl rtl simulation script /RD1055/simulation/vhdl/timing_verilog.do --> vhdl timing simulation script 4. RD1055/source/verilog/ACounter.v --> sourc
Platform: | Size: 1192960 | Author: cuiwei | Hits:

[Other] NAND_Controller

Description: flash controller VHDL语言，镁光芯片，包含ECC部分。-flash controller code
Platform: | Size: 27648 | Author: dingke | Hits:
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